Sensing circuitry generally has two modes: a self-timed mode and a clock-based mode. In a self-timed mode, the pulse width of a word line is generated based on a delay time with reference to an edge of a clock. For example, a word line WL is generated based on a delay time with reference to a rising edge of clock CLK. For another example, after a time delay TWLR from the rising edge of clock CLK at time TCLKR, the rising edge of word line WL is generated, and after a time delay TWLF from time TCLKR, the falling edge of word line WL is generated. In effect, word line WL has a pulse width with a duration of TWLF-TWLR.
Similarly, after a delay time TSAER from time TCLKR, the rising edge of signal SAE is generated, and after a delay time TSAEF from time TCLKR, the falling edge of signal SAE is generated. As a result, signal SAE has a pulse width with a duration of TSAEF-TSAER. In other words, both the rising and the falling edges of word line WL and signal SAE are triggered from the rising edge of clock CLK. In addition, the pulse width of both word line WL and signal SAE are determined by an internal self-reset circuitry, which is highly sensitive to process, voltage, and temperature (PVT) variations. The self-timed mode, due to semiconductor manufacturing process changes, has become more difficult to track well with PVT process variations. Additionally, because the self-timed mode depends on the clock frequency, it is difficult to debug when failures occur. An inaccurate delay time model, for example, for times TWLR, TWLF, TSAER, TSAEL, etc., can cause frequency independent failures.
In a clock-based mode, the rising edge of word line WL is triggered by the rising edge of clock CLK while the falling edge of word line WL is triggered by the falling edge of clock CLK. As a result, the clock-based mode consumes a large amount of power at lower frequencies because word line WL, at low frequencies in some approaches, is activated for a longer period of time. The rising edge of signal SAE, on the other hand, is triggered by the falling edge of clock CLK while the falling edge of signal SAE is triggered by the rising edge of clock CLK in the subsequent cycle. Because of the triggering mechanism that uses two clock cycles, the system that generates signal SAE is not efficient.
In some approaches in which both the self-timed mode and the clock-based mode are used, a manual switch is used to switch between the self-timed mode and the clock-based mode, which is complicated and requires human intervention. For example, when the clock frequency is changed from a higher to a lower frequency, a user would need to shut off the clock, change the clock setting, and turn on the clock again.
Like reference symbols in the various drawings indicate like elements.